An electrically programmable read only memory (EEPROM) having a memory cell of a floating gate type, metal-oxide-semiconductor (MOS) transistor is described in the Japanese Patent Application Laid Open No. 60-136996. An example of such an EPROM is shown in FIG. 1. Namely, a plurality of row lines 1.sub.1 to 1.sub.n and column lines 2.sub.1 to 2.sub.m are arranged in lateral and longitudinal lines, respectively. On intersecting portions of the row lines and a column lines, memory cells 3.sub.11 to 3.sub.1m, 3.sub.21 to 3.sub.2m, . . . each comprised of the floating gate type MOS transistor are arranged in a matrix form, respectively. More particularly, gates of groups of memory cells of the first to the n-th rows are connected to corresponding row lines 1.sub.1 to 1.sub.n, respectively. Similarly, drains of groups of memory cells of the first to the m-th columns are connected to corresponding column lines 2.sub.1 to 2.sub.m, respectively. Sources of all the memory cells are connected to the ground potential. One of the memory cells is designated by selecting one row line and one column line. One of the row lines and one of the column lines are selected by the row decoder 4 and column decoder 5, respectively. Only one of decoded signals R.sub.1 to R.sub.n output by the row decoder 4 is a logic "1". A row line corresponding to the signal of "1" level is selected. One of decoded signals C.sub.1 to C.sub.m output by the column decoder 5 is a logic "1". By the decode signals C.sub.1 to C.sub.m, one of enhancement type MOS transistors 6.sub.1 to 6.sub.m connected in series with the column lines 2.sub.1 to 2.sub.m is selected, i.e., is turned ON. Respective drains of transistors 6.sub.1 to 6.sub.m are commonly connected to constitute a common connection node A. This node A is connected to a power supply V.sub.c of, e.g., 5 volts, through an enhancement type MOS transistor 12. The gate of the transistor 12 is connected to an output node B of an inverter I. This inverter I is comprised of a depletion type MOS transistor 13 and an enhancement type MOS transistor 14. The gate of the MOS transistor 14 serving as the input terminal of the inverter I is connected to the node A. The output terminal (node B) of the inverter I is further connected to the gate of an enhancement type MOS transistor 15 connected between the node A and a data sense node C. The data sense node C is connected to the power supply Vc through a load transistor 16. The gate of the load transistor 16 is also connected to the power supply Vc. A sense amplifier 17 is connected to the data sense node C. Data stored in the memory cell is detected by the sense amplifier 17.
In the semiconductor memory device thus constructed, it is now assumed that row line 1.sub.1 and column line 2.sub.1 are selected by the row and column decoders 4 and 5, respectively. So, the memory cell 3.sub.11 is selected. It is further assumed that the threshold voltage of the selected memory cell 3.sub.11 is low. No electron is injected into the floating gate of the memory cell 3.sub.11. In this case, Since this memory cell 3.sub.11 is turned ON, the column line 2.sub.1 is discharged through the memory cell 3.sub.11. Then, data D of "0" level is detected by the sense amplifier 17. In contrast, if it is now assumed that the threshold voltage of the memory cell 3.sub.11 is high, electrons are injected in the floating gate of the memory cell 311. In this case, if this cell is selected, it is not turned ON. For this reason, column line 2.sub.1 is charged through load transistors 12 and 16. Then, data of "1" level is detected by the sense amplifier 17.
However, the semiconductor memory device constructed as above has the drawback that the readout speed of "0" data is slow. This will be described in detail in relation to the operations of respective elements.
It is initially assumed that, e.g., a memory cell 3.sub.11 is selected by the row decoder 4 and the column decoder 5. Let suppose that this memory cell 3.sub.11 stores "0" data and is turned ON. Thus, the column line 2.sub.1 is discharged through the memory cell 3.sub.11, resulting in a low potential on the node A. As the result of the fact that potential on node A is lowered, a potential on node B of the output terminal of the inverter I rises. As the result of the fact that the potential on the node B rises, the resistance of the transistor 15 is lowered. For this reason, the potential on the node C becomes closer to the potential on the node A through the transistor 15. The sense amplifier 17 detects that the potential on the node C is lowered. That is, the sense amplifier 17 detects the "0" data stored in the memory cell 3.sub.11.
It is now assumed that a memory cell 3.sub.21 is selected. It is further assumed that this memory cell 3.sub.21 stores "1" data and is turned OFF even though if it is selected. The column line 2.sub.1 is charged through the transistors 12 and 16. At the beginning of the charging operation, the output of the inverter I is "1" level. For this reason, at the beginning of the charging operation, the column line 2.sub.1 is charged through the transistors 12 and 16. Thus, the potential on the node A is rapidly raised. The output potential of the inverter I is lowered in a direction of "0" level with the rising of the potential on the node A. Thus, the transistors 12 and 15 are turned OFF. As the result of the fact that the transistor 15 is turned OFF, the node C is charged through the transistor 16. The potential on the node C rises so that it is a logic "1". This "1" is detected by the sense amplifier 17.
The transistors 12 and 15 are turned OFF when the potential difference between the node A and the gates of the transistors 12 and 15 is less than the threshold voltages of the transistors 12 and 15.
However, in the inverter I, there is a delay time between the input and the output thereof. Consequently the potential of the node A would be a higher potential than a value obtained by subtracting the threshold voltage of the transistors 12 and 15 from the gate potentials of the transistors 12 and 15, when column line 2.sub.1 is charged.
The above-mentioned charging of the column line will be explained in more detail with reference to FIG. 3 in addition to FIG. 1. It is now assumed that the threshold voltages of the enhancement type transistors 12 and 15 are both represented by Vth. As previously described, in the case of the charging of node A, transistors 15 and 12 are turned OFF when the potential on node B is equal to sum of the potential on node A and the threshold voltage Vth. When transistors 15 and 12 are turned OFF, the result is no charge path in node A. As a result, there is no increase of potential more than the potential at that time. However, from a practical point of view, because of a delay in the operation of the inverter I, there occurs a delay in change of the potential of node B with respect to the change of the potential of node A. Generally, the potential on node B is lowered according to the rising of the potential on node A. Namely, when viewed from DC level, the potential on node B is determined relative to the potential on node A. However, as shown in FIG. 2, when the column line (the node A on the input side of the inverter I) is being charged in a manner of the AC charge operation, the potential on node B of the output of the inverter I varies in a delay time with respect to change of the potential on the node A. It is now assumed that, e.g., the potential on node A is equal to a value of X(V) at time t.sub.0 and then changes to a value of (X+.alpha.)(V) at time t.sub.1 . The potential Y.sub.1 (V) on node B at time t.sub.1 is not determined by the potential on the node A at time t.sub.1 without delay time. Because of the load capacitance existing on node B of the output of the inverter I and the response time of the transistor, the response speed of the inverter I is delayed. For this reason, the potential Y.sub.1 on the node B at time t.sub.1 corresponds to a potential which is viewed from the DC level with respect to the potential on the node A, e.g., at time t.sub.0. For example, at time t.sub.1 of FIG. 2, the potential on node B is equal to "the potential on node A plus Vth". However, the potential Y.sub.1 on node B at the time t.sub.1 is a potential which is viewed from the DC level with respect to the potential of X(V) on node A at the time t.sub.0. For this reason, node A is over charged. Namely, it is now assumed that transistors 12 and 15 are turned OFF, so the charging of the node A is stopped. However, the potential of node B which is viewed from the DC level with respect to the potential (X+.alpha.) on the node A at the time t.sub.1 appears at time t.sub.2. For this reason, a potential relationship of the nodes A and B at the time t.sub.2 and times subsequent thereto deviates from a relationship defining a critical and minimum DC potential required in order to allow the transistor 15 to be turned OFF. In the case of reading the data "0", even if the discharging of the node A is started, as long as the transistor 15 is not turned ON, the potential on node C is not lowered. For this reason, the sense amplifier cannot sense new data. If the charging of the column line is stopped in a manner that the relationship of the potentials of nodes A and B is in correspondence with that shown prior to t.sub.0 in FIG. 2, transistor 15 is turned ON by a slight discharging of the node A, so that a potential on the node C is rapidly discharged. However, when the relationship between the potential of the node B and the potential of the node A changes to the relationship as shown at time t.sub.2 of FIG. 2, the memory cell must discharge a large quantity of charges in the column line in order to turn on the transistor 15. Furthermore, a large capacitance exists on the column line. For this reason, a greater quantity of charges must be discharged in order to turn on transistor 15. Therefore, the discharging time is prolonged. For these reasons, particularly when it is necessary to discharge charges on the column line, there results the drawback that the data readout speed becomes slow. For this reason, in the prior art, in order to provide a high speed response of the inverter I, the current drivability of the inverter I was enhanced. However, when an approach to enhance the current drivability is employed, there is a new drawback in that the power dissipation in the inverter I is increased.